A typical flash memory device includes a memory array having a large number of memory cells arranged in blocks. Each of the memory cells includes a field effect transistor having a control gate and a floating gate. The floating gate holds a charge and is separated from source and drain regions in a substrate by an oxide. Each memory cell can be electrically charged by electrons injected onto the floating gate. The charge may be removed from the floating gate by an erase operation. The data in flash memory cells are thus determined by the presence or absence of charge in the floating gates.
It is a trend in memory devices to scale down the device size for packing density and cost. In a conventional flash memory structure, it is a challenge to shrink the word line length due to conflicting factors. For example, for a typical split gate flash memory device, a memory gate of the device depends on the control gate of the device. If scaling down the control gate, the memory gate thickness may become too thin. An associated ion implantation may penetrate the thin memory gate, causing the memory gate to not long work.
Accordingly, what is needed are a method and a device that address the above issues.